AMD to support Intel AVX instructions

[Mickie]

Doing the math on SSE compatibility

Chip designer and erstwhile maker Advanced Micro Devices will support a bunch of Advanced Vector Extensions (AVX) instructions, part of the family of extended Single Instruction, Multiple Data (SIMD) instructions for x64 chips that Intel announced last year.

The move, announced today, will make AMD's Opteron, Athlon, and Turion chips a bit more compatible with the Core and Xeon chips from Intel, making the lives of software developers a bit easier because they won't have to tune applications to take advantage of two different sets of vector extensions.

Intel first introduced Streaming SIMD Extensions (SSE) for its processors back in 1999 with the Pentium III processors, and these SSE instructions were a reaction to the multimedia processing instructions that AMD added to its x86 chips called 3DNow.

Intel continued to add SSE instructions over time, and was at the SSE 4.1 level in the "Penryn" Core 2 processors and has added some more instructions with the SSE 4.2 set with the "Nehalem" cores used in the i7 desktop and Xeon 5500 server processors.

Back in August 2007, as it became apparent to AMD that Intel had finally woken up from its capitalistic and technological slumber, AMD opened up a set of Streaming SIMD Extensions (SSE) for its x64 processors that, in a cheeky move, it called SSE5. These comprised 128-bit extension to the 64-bit X64 architecture of the Opterons, including 46 base instructions and 124 additional instructions that were to be implemented in AMD's "Bulldozer" processor cores, slated for 2009 back then but now coming out in 2011. (There are already some 128-bit instructions in the Opterons, such as the 128-bit floating point units that made their debut with the "Barcelona" Opterons.)

While AMD's proposed SSE5 instructions would speed up certain algorithms used in high performance computing, multimedia and security applications, SSE5 is not a superset of Intel's SSE4 instructions, even though there is quite a bit of overlap. And that means programmers and their compilers having to be mindful of the underlying instruction set when they optimize their code for a Xeon or Opteron chip.

Last April, as part of its SSE instruction set, Intel put forward a proposal for a bunch of new instructions, including a set of instructions collectively called Advanced Vector Extensions (AVX), which include XOP (for eXtended Operations), CVT16 (half-precision floating point converts), and FMA4 (four-operand Fused Multiply/Add).

While AMD had similar functions in its SSE5 proposal, Dave Christie, senior chip architect at AMD, said in a blog posting that AMD is trying to strike a balance between innovation and standardization and that is why it has embraced Intel's way of implementing these instructions. (The blog post has some details on the instructions, and if you really want to get into it, read the specification here (pdf). Knock yourself out.) Christie says that a version of the AMD64 SimNow simulator will support these Intel instructions "in very short order".

AMD says that the AVX instructions will make their way into the Bulldozer cores in 2011. If you need a refresh on the updated AMD processor roadmap, see our previous coverage here. ®

http://www.theregister.co.uk/2009/05/06/amd_does_avx/

[Mickie]

A look at AMD's AVX and XOP
Analysis The first fusion hints
By Charlie Demerjian
Monday, 11 May 2009, 20:04

A FEW DAYS AGO, AMD announced that it would support Intel's AVX instruction set rather than continuing on with SSE5. This stops any fragmentation and lets the best implementation win.

SSE5 is a superset of AVX. AMD put the bits not covered in another ISA called XOP, so with one exception, SSE5 became AVX + XOP. When Sandy Bridge and Bulldozer come out, we will get a chance to see how each one is done, and what the various strengths and weaknesses are.

The one difference seems pretty silly. Intel updated the AVX spec in January and changed an instruction called Fused Multiply Add (FMA) from a four operand instruction to a three operand, lets call them FMA4 and FMA3 respectively.

FMA is an operation that multiplies two numbers then adds it to a third. It looks like (A * B) + C. The difference between the -3 and -4 versions is where the result ends up. If you think of A, B and C as registers, FMA3 is (A * B) + C = C while (A * B) + C = D. AMD's version puts the result in a fourth register, Intel's overwrites register C.

If you ask AMD, it will say that FMA4 saves you a copy after the operation. Intel will likely say that you don't need to move the result. One thing is clear though, if you need to do a lot of operations, like (A * B) + constant, the AMD method will save you a bunch of cycles. That said, there are technical tradeoffs to both methods.

This one op defines the differences between Intel's AVX and AMD's AVX, and it is something that any compiler can easily work around. What will be interesting is seeing if Intel's professed compiler detente will take this into account. Time will tell.

The rest of SSE5 ended up in a set of opcodes called XOP. You can read about them in an AMD blog here. A few interesting ones to check out, Integer Multiply/Accumulate (IMA), Byte Permute (BP), Bit-wise Conditional Move (BCM), and Half-Precision Convert (HPC).

IMA is interesting because it allows you to do a traditionally FP calculation with 128-bit integers. The next two, BP and BCM are somewhat similar. BP takes bytes from two 16-bit vectors and copies them to a destination using a third vector as a mask. It can also twiddle the bytes as it copies them. BCM is similar, but it uses bits, not bytes, and obviously you can't twiddle a single bit much.

The last one, HPC, has it's own extension called CVT16, and that carries a CPUID flag as well. The short story is that it will convert between half and full precision on loads and stores with control over rounding and denorms.

This may seem like a yawner, but stop and think about this, why would one single instruction need it's own ISA name and CPUID flag? Well, the instruction is very useful in graphics and setting up pixels. Top it off with denorms being a part of DX11 and... and it doesn't take a genius to see the beginnings of the fusion ISA.

All in all, AMD did the right thing here in preventing ISA fragmentaion, and a mild slap on the wrist to Intel for changing the spec so late in the game. That said, AMD seems to have the better ISA on paper, but paper is not CPU performance.

The real test will be in the products that use them. Did one side implement it as a two pass 128-bit operation and the other 256-bit one pass? Is one a vastly better implementation? Does FMA4 do a lot better performance-wise than FMA3? These are open questions, and we will be unlikely to know the answer for sure until early 2011. µ
Click here to find out more!

http://www.theinquirer.net/inquirer/...ok-amd-avx-xop

AMD ne odustaje od SSE5, ali mu dodaje AVX pa ce podrzavati sve. Intel na to odgovara tako sto menja jednu instrukciju. Fused Multiply Add je promenjen, ali ne toliko da bude nekompatibilan. AMD ce biti u prednosti sto se tice instrukcija.