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Intel planira da namerno ogranici OC Sandy Bridge-a

Information provided by Intel in its own presentations about its upcoming mainstream LGA1155 Sandy Bridge CPUs appears to confirm the company has designed the CPUs to deliberately limit overclocking.

A video leaked to HKEPC and posted on YouTube (see from 2mins onwards) confirms the fact that only a 2-3 per cent OC via Base Clock adjustments will be possible. This is because Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc) to a single internal clock generator issuing the basic 100MHz Base Clock.

This clock gen is integrated into the P67 motherboard chipset and transmits the clock signal to the CPU via the DMI bus. This means there's no need for an external clock generator that used to allow completely separate control of all the individual hardware.

When you're overclocking, you want to be able to push certain frequencies, such as the Base Clock and memory clock, but leave others, such as SATA, completely stable as they're very sensitive to adjustment. Current motherboards allow multiple bus speeds because external clock generators are programmable via the BIOS.

According to one Taiwanese motherboard company, on a Sandy Bridge system, the fact that all the busses are linked means that turning up the Base Clock by just 5MHz caused the USB to fail and SATA bus to corrupt...

Izvor: bit-tech